The Backbone of The Internet of Things

As the Internet of Things (IoT) grows from six billion connected devices today to an estimated 20 billion by 2020, global data traffic is expected to increase nearly fivefold, passing a new milestone figure of two zettabytes by 2019. [1] (One zettabyte is equal to a billion terabytes.) ClariPhy engineers are delivering next-generation communication architectures fabricated on the most advanced technology process nodes to enable the fabric of networks across the globe to handle rapid increases in data traffic without compromising quality of service. For these state-of-the-art designs to meet stringent performance and quality (reliability) requirements, the power delivered to the transistors inside these ultralarge system-on-chip (SoC) designs has to be robust across the chip and across all operating conditions. To meet these pecifications, the global power distribution network (PDN) must be constructed with awareness of requirements on the chip (e.g., voltage drop, routing resources), the package (e.g., package plane, decaps) and the PCB (e.g., voltage regulator module placement).

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